1. Technical Field of the Invention
The present invention relates to an evaluation method of a thin film transistor or a method of manufacturing the same, or a method of manufacturing a semiconductor device having the thin film transistor. Further, the present invention relates to a program or a recording medium to control a quantity of impurities to be added based on the evaluation method.
2. Description of the Related Art
A characteristic deterioration phenomenon due to hot carriers is given as a physical phenomenon about life expectancy in a semiconductor element typified by a thin film transistor (hereinafter, referred to as a TFT). A hot carrier is caused by a hole and an electron in a nonequilibrium state that exceeds a temperature of a lattice system, and particularly, the electron is called a hot electron. As a size of a device becomes smaller, a local electric field becomes larger. A malfunction or a decrease of an operation function of a semiconductor device, or reduction of drain current to drain voltage is caused by the thus generated hot carriers, which makes a device property or performance of a semiconductor device deteriorate.
Herein, a phenomenon of deterioration by a hot electron is described. When a semiconductor element is operated, a high electric field region is formed in a drain region, specifically, in the vicinity of a junction region of a channel forming region and the drain region. The electron that has flowed into this high electric field region becomes a hot electron having a extremely high energy. At this time, a portion of the hot electrons are injected into a gate oxide film, or generate an interface level on Si—SiO2 interface, thereby changing an element characteristic. In addition, there is not only a hot electron of the channel electron but also a substrate hot electron.
Further, there is injection of a carrier which is generated by collision ionization or avalanche multiplication into an oxide film as a hot carrier (Drain Avalanche Hot Carrier: DAHC) and a hot electron injection generated by secondary collision ionization (Secondarily Generated Hot Electron: SGHE). Note that details thereof are described in submicron device II p. 121 to 142 (written by Mitsumasa Koyanagi, Maruzen Co., Ltd.).
As a method for preventing a deterioration due to such a hot carrier, it is known a Lightly Doped Drain (LDD) structure TFT which is provided a region added an element of impurity at low concentration (a first low concentration impurity region) between a channel forming region and a source region or drain region.
Further, as a method for preventing performance reduction due to parasitic resistance of an LDD region, it is known a Gate-Overlapped LDD (GOLD) structure TFT which is arranged an gate-overlapped region overlapping LDD region with a gate electrode across a gate insulating film (a second low concentration impurity region). It is known that high electric field of a drain vicinity is relieved to be prevented hot carrier injection by using these structure like this, which is effective for preventing a deterioration phenomenon.
The reliability of this GOLD structure TFT greatly depends on an impurity concentration in a gate-overlapped region. When an impurity concentration of an gate-overlapped region is high, a strong electric field generates on an interface of a channel forming region and the gate-overlapped region, a generation quantity of hot carriers becomes large, and characteristics deterioration of a TFT such as on-state current reduction is serious.
On the other hand, in case that an impurity concentration of a gate-overlapped region is reduced to some extent, as an electric field intensity of an interface between a channel forming region and a gate-overlapped region decreases, an electric field intensity of an interface between a drain region and the gate-overlapped region increases. However, it is desirable that a maximum of an electric field becomes small and characteristics deterioration of a TFT becomes small.
However, when the impurity concentration of the gate-overlapped region is further lowered, a strong electric field generates on the interface between the drain region and the gate-overlapped region. Thus, even when the impurity concentration of the gate-overlapped region is low, characteristics deterioration of a TFT increases. Therefore, it is important to grasp an impurity concentration of a gate-overlapped region more precisely to improve reliability of a semiconductor element.
And so, a method for estimating an impurity introduction in consideration of a dosage dependence and an impurity concentration distribution of a thermal diffusion area by a simulation has been used in an LSI field. This is a method for simulating by a step including a calculation of an impurity concentration distribution of an impurity diffused region based on a total amount of introduced impurities, in the case where impurities are introduced into a semiconductor substrate, and the impurities are diffused by a heat treatment to obtain the impurity diffused region. (Refer to Patent Document 1: Japanese Patent Laid-Open No. Hei 8-139044.)
Specifically, a method for forming only a lower conductive film over a semiconductor film and then measuring resistance of a measurement element that has been formed by adding impurities thereinto, in order to grasp an impurity concentration of a gate-overlapped region (Lov region) that is overlapped with only the lower conductive film of a gate electrode has been employed in a field of a thin film transistor. In this case, only an element for measuring resistance of a gate-overlapped region is formed over another substrate, or the number of masks is increased to form an element for measuring resistance in a portion of substrate.
However, it is difficult to precisely measure resistance of a Lov region in this method, since a gate electrode of a gate-overlapped region formed in a self-alignment process is subjected to taper-etching and anisotropic etching, as well as increasing the number of the steps. This is because a TFT and a measurement element cannot be formed over the same substrate and in the same process.
Thus, it is an object of the present invention to provide a method for manufacturing an element for measuring Lov resistance, an evaluation method using the element for measuring Lov resistance, an element substrate and a panel having the element for measuring Lov resistance.